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D Flip-Flops and JK Flip-Flops | 74LVX273

Low Voltage Octal D-Type Flip-Flop

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Overview

The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR#) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR# input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.

  • This product is general usage and suitable for many different applications.
  • Input voltage translation from 5V to 3V
  • Ideal for low power/low noise 3.3V applications
  • Guaranteed simultaneous switching noise level and dynamic threshold performance

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74LVX273M

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Obsolete

CAD Model

Pb

A

H

P

SOIC-20W

751BJ

1

260

TUBE

1080

N

Octal D-type

8

2

3.6

14.5

4

Price N/A

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74LVX273MTC

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Obsolete

CAD Model

Pb

A

H

P

TSSOP-20

948AQ

1

260

TUBE

1825

N

Octal D-type

8

2

3.6

14.5

4

Price N/A

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74LVX273MTCX

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Active

CAD Model

Pb

A

H

P

TSSOP-20

948AQ

1

260

REEL

2500

N

Octal D-type

8

2

3.6

14.5

4

$0.324

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