Name: Clock Driver, 2:1:9 Differential HSTL / PECL to HSTL, 3.3 V
Brand: Clock Driver, 2:1:9 Differential HSTL / PECL to HSTL, 3.3 V
SKU: MC100EP809

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Clock Driver, 2:1:9 Differential HSTL / PECL to HSTL, 3.3 V

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Overview

The MC100EP809 is a low skew 2:1:9 differential bus clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are one differential HSTL and one differential LVPECL. Both input pairs can accept LVDS levels. They are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous so that the outputs will only be enabled/disabled when they are already in LOW state.

The MC100EP809 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. The MC100EP809 output structure uses open emitter architecture and will be terminated with 50 to ground instead of a standard HSTL configuration. To ensure that tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.

Designers can take advantage of the EP809's performance to distribute low skew clocks across the backplane of the board. HSTL clock inputs may be driven single-end by biasing the non-driven pin in an input pair.

Applications

Clock distribution

Features

100 ps Typical Device-to-Device Skew
15 ps Typical Within Device Skew
HSTL Compatible Outputs Drive 50Ω to Ground with no Offset Voltage
Maximum Frequency > 750 MHz
850 ps Typical Propagation Delay
Fully Compatible with Micrel SY89809L
PECL and HSTL Mode Operating Range: V_CCI = 3 V to 3.6 V with GND = 0 V, V_CCO = 1.6 V to 2.0 V
Open Input Default State
Pb-Free Packages are Available

Material Composition

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Input / Output Ratio

Input Level

Output Level

V_CC Typ (V)

t_JitterRMS Typ (ps)

t_skew(o-o) Max (ps)

t_pd Typ (ns)

t_R & t_F Max (ps)

f_maxClock Typ (MHz)

f_maxData Typ (Mbps)

Reference Price

MC100EP809MNG

Active

QFN-32

488AM

260

TUBE

Buffer

2:1:9

LVDS

HSTL

3.3

1.4

0.85

600

750

Price N/A

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Drivers & Fanout Buffers | MC100EP809

Clock Driver, 2:1:9 Differential HSTL / PECL to HSTL, 3.3 V

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