Name: 3.3 V / 5.0 V ECL ÷路4 Divider
Brand: 3.3 V / 5.0 V ECL ÷路4 Divider
SKU: MC100EP33

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3.3 V / 5.0 V ECL ÷路4 Divider

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Datasheet

CAD Model

Overview

The MC10/100EP33 is an integrated divide by 4 divider. The differential clock inputs.

The V_BB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB and V_CC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, V_BB should be left open.

The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EP33's in a system.

The 100 Series contains temperature compensation.

Applications

Phase Lock Loops

Features

320ps Propagation Delay
Maximum Frequency > 4 GHz Typical
PECL Mode Operating Range: V_CC= 3.0 V to 5.5 V with V_EE= 0 V
NECL Mode Operating Range: V_CC= 0 V with V_EE= -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output will default LOW with inputs open or at V_EE
V_BB Output
Pb-Free Packages are Available

Material Composition

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Package Type

Case Outline

MSL Type

MSL Temp (掳C)

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Container Qty.

Type

Input Level

Output Level

V_CC Typ (V)

f_Max Typ (MHz)

t_pd Typ (ns)

t_R & t_F Max (ps)

Reference Price

MC100EP33DG

Active

SOIC-8

751-07

260

TUBE

Divider

ECL

4000

0.38

200

Price N/A

MC100EP33DTG

Active

TSSOP-8

948R-02

260

TUBE

100

Divider

ECL

4000

0.38

200

Price N/A

MC100EP33DTR2G

Active

TSSOP-8

948R-02

260

REEL

2500

Divider

ECL

4000

0.38

200

Price N/A

MC100EP33MNR4G

Active

DFN-8

506AA

260

REEL

1000

Divider

ECL

4000

0.38

200

Price N/A

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Arithmetic Functions | MC100EP33

3.3 V / 5.0 V ECL ÷路4 Divider

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